Software & Tools
Configure IP with ARChitect®
Powerful Design Tool Automates Configurability of ARC Multimedia Subsystems and Cores
In minutes, ARChitect generates a highly differentiated, proprietary ARC-Based™ subsystem or processor that consumes less power and has fewer transistor gates than can be created using a “fixed architecture” alternative.
Using ARChitect's GUI-based development environment and simple drag-and-drop menus, system-on-chip (SoC) designers select from 20,000+ pre-configured options and/or create custom instruction extensions that are optimized to the 16- /32-bit ARCompact™ ISA.
Benefits
Differentiate to Keep the Competitive Edge
- Add and remove features using the ARChitect tool’s drag-and-drop GUI
- Optimize for smaller die size, lower power or best performance
- Add custom instructions, registers and other logic to dramatically increase performance
Reduce Time to Market and Minimize Risk
- Quickly iterate through multiple system configurations to determine the best options for your requirements
- Automatically create verified RTL and synthesis scripts that are compatible with industry-standard design flows
- Automatically create a complete set of downstream development tools for the user's customized subsystem
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ARChitect® IP Configurator Block Diagram
Click to view larger image.
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Configurability Optimizes Die Size and Power
Designers can include features they need and remove features they do not need for their application using the ARChitect tool’s drag-and-drop GUI. Configuration options include features around the subsystem and core such as type and size of caches, interrupts, DSP subsystem, timers and debug components, as well as features within the core such as type and size of core registers, address widths, and instruction set options. Performance and die size tradeoffs are quickly accomplished, resulting in an optimized solution. The resulting design will be smaller and lower power than designs with fixed configurations.
Significant gains in application efficiency can be achieved by defining custom processor extensions. Using ARChitect's four step extension wizard, the designer can add instructions, registers and other logic to dramatically reduce the number of cycles required to execute inner loops and other critical code segments. The result is higher application performance and/or lower device frequency and power than can be achieved with fixed instruction set cores.
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Automation Optimizes the Development Process
The ARChitect tool produces verified RTL and synthesis scripts that are compatible with industry-standard design flows. In addition, it generates files and scripts which create a complete set of downstream development tools for the user's customized subsystem, including test bench, simulators, compiler/debugger, prototyping platform and documentation. In this way, ARChitect streamlines design projects, reducing time-to-silicon and risk.
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