Software & Tools

ARC® VTOC® Tool

100% Cycle Accurate Modelling of ARC and/or Non-ARC IP

ARC® VTOC® products use the technology behind the ARC xCAM modeller to automatically provide 100% cycle accurate C++ and SystemC models of customers’ ARC and/or non-ARC IP written in Verilog or VHDL. Since the models are pure software and can be compiled to binary, they also are ideal for secure shipment of IP models to third parties.

• Reuse of legacy RTL IP in C++/SystemC architectural exploration of new designs. This is ideal for next generation Electronic System Level (ESL) design flows and tools.
• Creation of virtual platforms for early development and system verification of complex SoCs with their associated software before real silicon is available.

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| Hightlights | The VTOC Suite |

Highlights

Fully Cycle Accurate
Models of complete SoCs (including ARC and/or non-ARC IP) are generated automatically. Code for the complete SoC can be tuned on actual processor configurations, and hardware can be tested and verified. Furthermore, exact VTOC models match the SoC design so there is no risk of the model and RTL becoming out of sync.

Flexible Model Use
Software models can be deployed anywhere, allowing engineers in different locations to easily iterate and test code algorithms and design configurations, and to find right code size/performance tradeoffs.

Highly Productive Integrated Solution
ARC VTOC C++/SystemC models can be used standalone within custom development and system verification environments. VTOC models also are integrated with next generation Electronic System Level (ESL) tools such as CoWare Platform Architect. Detailed cycle information is provided to guide assessments and profiling, or SystemC models can connect to wider co-development tool flows to help productivity. Users can run the same software on different models and determine which SoC configuration provides best software performance.

Shortens Design Time
ARC VTOC models enable architectural design with legacy RTL, early development of software, early verification of SoC with software, and fast hardware iterations.

Efficient ESL Architectural Exploration
ARC VTOC models can be used in a standalone OSCI SystemC environment or integrated with industry standard tools such as CoWare Platform Architect.

With VTOC, an SoC designer can eliminate the need to manually recreate system models of existing IP, using instead models synthesized and validated directly from the RTL in a repeatable manner. This provides high performance reuse of existing RTL, enabling architectural modelling of the complete design.

Virtual Platforms for Early Software Development and System Verification
With VTOC an SoC designer can eliminate the need to manually create accurate models of implementation RTL.

VTOC source C++ models are ideal “Virtual Platforms” for integration with software development tools, while VTOC SystemC models provide a plug-n-play integration with tools such as CoWare Platform Architect. Integration of the models with hardware debug environments such as Novas Verdi and Cadence SimVision ensure any problems can be easily communicated between software and hardware teams.

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The VTOC Suite

ARC® VTOC® is a comprehensive suite of software products that support the move to electronic system level (ESL) design environments.

• VTOC Generate
  VTOC Generate takes designs in Verilog, VHDL or a mixture of the two and synthesizes a 2-value cycle accurate C++ or SystemC model that can be targeted automatically for use in C++, SystemC, or HDL environments under Microsoft Windows or Linux.
• VTOC Validate
  VTOC Validate functionally verifies the C++ model created by VTOC Generate against the behaviour of the original RTL to enable early identification of potential problems in initialization, and use of 4-value simulation vs. 2-value synthesized model behaviour.
• VTOC RunTime
  VTOC RunTime provides comprehensive command line interfaces and APIs to access and debug the running model.
• VTOC Export
  VTOC Export provides controlled distribution of the secure C++ models created by VTOC Generate for use as evaluation platforms. Each export model has the performance of a VTOC model, with the security of binary compiled code and the ability to execute in C++, SystemC, and HDL environments under Microsoft Windows and Linux.

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