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Azuro, Inc.
Azuro provides an optimized low power methodology for ARC® customers designing chips for power-sensitive embedded applications. Azuro’s PowerCentric™ methodology uniquely combines clock gating and clock buffering capabilities into a unified low power clock implementation solution, which completely replaces clock tree synthesis in existing EDA design flows. Using PowerCentric, ARC customers can reduce power consumption of the ARC-Based™ logic by more than twenty percent.
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Electronic Design