Products & Solutions
ARCŪ Energy PRO Core Family
32-Bit Configurable CPU Cores Reduce Power Consumption by
75% or More
ARC® Energy PRO configurable cores are the market's most energy-efficient 32-bit CPUs/DSPs, providing best-in-class solutions for power-constrained applications in consumer, mobile communications and medical markets. Featuring advanced system-level power-management capabilities, they are based on a code-compatible
evolution of ARC's successful 600 Series cores.
Content On This Page
| Benefits | Applications | Block Diagram
| Architecture |
| Customized Instruction Extensions | Power-Aware Software |
Benefits
Ultra-Low Power
ARC Energy PRO cores implement sophisticated techniques such as dynamic voltage and frequency scaling (DVFS) across your entire SoC. Controlled by a dedicated power management unit (PMU), Energy PRO cores reduce consumption by 75% or more in typical applications.
Configurable
ARC's unique configurable architecture allows the designer to choose exactly which function blocks are needed within the core, and their characteristics. Energy PRO products are configurable to be the industry's smallest, lowest-power licensable cores.
Programmable
ARC's cores are designed for easy programmability, implementing a linear C/RISC-type programming model via a comprehensive development and programming toolset. Rich software tools and the power-aware MQX operating system put control of Energy PRO's power-saving features directly in the programmer's hands.
Efficient
A core that fits the application makes the most of precious chip area and system resources. ARC Energy PRO cores can even include custom CPU instructions, providing the perfect fit to any application and further enhancing energy efficiency. And they allow zero-overhead switching between 16-bit and 32-bit instruction sets, reducing external memory footprint.
Easy
ARC cores are made for real-life use, by real-life designers. A full range of ARC proprietary and third-party tools and library components assist development of hardware and software, and facilitate genuine co-design for faster time-to-market.
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ARC Energy PRO Core Applications
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ARC Energy PRO Block Diagram
Click here to view larger image.
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ARC Energy PRO Core Architecture
CPU Architecture
ARC Energy PRO 32-bit configurable processors employ a highly-efficient five stage pipeline, delivering up to 1.3DMIPS/MHz with ultra-low power consumption and industry-leading die size.
Designed for use in battery-powered and other power-constrained appliances, the Energy PRO architecture deploys four advanced energy-saving technologies: functional clock gating; architectural clock gating; power shut-off; and dynamic voltage and frequency scaling (DVFS). All of these function under the control of a dedicated power management unit (PMU). An external interface allows the designer to apply these techniques not just within the CPU, but across the entirety of an SoC design.
By combining the most appropriate energy-saving strategies on a per-block and per-subsystem level, ARC Energy PRO cores allow designers to define multiple power management modes. These can be selected as appropriate to ensure that the device uses the minimum possible power, while still providing the required performance.
Energy PRO cores also include flexible memory options to address a wide range of processing needs. These include single-cycle closely coupled memories (CCMs) for instructions and data, as well as configurable instruction and data cache, and a memory protection unit (MPU). External access is via multiple 32-bit ports, including main memory, auxiliary registers and CCMs. BVCI , AHB and AXI configuration options are supported.
ARCompact™ ISA
Energy PRO uses the ARCompact instruction set architecture (ISA), with supplementary instructions specifically designed to make best use of the capabilities of the PMU, and of the available energy-saving techniques.
As with all of ARC's cores, designers can improve code density by up to 40 percent thanks to the ability to mix 16- and 32-bit instructions freely without overhead.
Highly Configurable
ARC's concept of configurability allows optimization of core designs on three distinct levels, within a single, coherent architecture. First, designers can choose the required execution blocks: for instance cache, FPU and DSP. Second, they can tune the parameters of those blocks: for instance cache size and CPU register file size. Finally, they can define custom instructions, additional core and auxiliary registers, custom condition codes and co-processor interfaces.
In addition to performance, size, power and cost trade-offs, the ARC configurable architecture therefore delivers unrivalled design flexibility.
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Customized Instruction Extensions
In common with all of ARC's configurable cores, the Energy PRO cores offer designers the opportunity to define custom instructions to accelerate critical parts of their applications. The resultant gains can be used to improve performance by as much as 100 times, to reduce required clock frequencies, or to free up other core resources and increase application flexibility. Other user defined extensions may include co-processor interfaces, auxiliary registers, and condition codes.
Powerful DSP Capabilities
The Energy PRO series includes powerful options that enable the core to perform DSP functions, without the need to add separate execution blocks or co-processors. These are implemented within the RISC pipeline, with performance of up to 1.4GMACS in a 90nm process.
Floating Point Instructions
ARC™ FPX Floating Point Extensions add high performance single and double precision floating-point capabilities to the EP series CPU itself, substantially accelerating execution with little increase in power consumption or die size. These IEEE-compliant instructions and library functions provide the power required for graphics and image processing routines, complex computations or advanced control algorithms.
By making use of the main processor pipeline and data paths, FPX extensions can be built with as few as 13K gates. As a result FPX is over five times more efficient in terms of gate usage than typical FPU co-processors.
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Power-Aware Software
Ease of Design
The ARC Energy PRO architecture is designed for ease of design using standard EDA flows and semiconductor libraries. Software teams will find the architecture equally user-friendly, with a host of facilities that give programmers high-level control over the power management features of an ARC-based SoC.
All of this builds on ARC's outstanding support offering covering hardware configuration and verification, software design and debug, and genuine system-level co-design.
Industry-Standard EDA Flow
Designers deploying Energy PRO cores can use any industry-standard RTL-to-GDSII EDA flow. From design inception, the ARChitect™ Processor Configurator captures the low-power design intent. This can be used throughout the flow, right up to tape-out, allowing accurate simulation of power-down modes, correct insertion of features such as isolation cells and level shifters, and use of place-and-route tools that accommodate the use of voltage islands.
A fully integrated reference design methodology (RDM), developed in collaboration with Cadence Design Systems and Virage Logic, offers designers a simple, automated, validated development flow.
Industry-Leading Development Environments
Like other ARC cores the Energy PRO series is backed with the best development tools on the market today:
- The ARC MetaWare Development Toolkit, including C/C++ compiler, advanced debugger, integrated profiler and Eclipse IDE
- GNU suite, including gcc and gdb
- Green Hills Software Multi Suite
Software developers can harness Energy PRO power management features via a software API that can be incorporated into an operating system or used directly by an application. Programming support is integrated via ARC's MetaWare® development tools.
The result is tight control of power budgets. Core voltage and clock rate can be scaled according to the requirements of individual threads; or the core may be shut down when no threads are running.
Modeling Tools
ARC provides a wide range of modeling tools to allow software development to begin as soon as the core hardware configuration has been defined.
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ARC xCAM enables the ARChitect IP Configurator to automatically generate cycle accurate models (CAMs) within minutes of a configuration being finalized. Executing at between 40kHz to 60kHz, xCAM models enable a genuinely iterative design approach compatible with SystemC
- Pre-built CAMs are available for common ARC EP configurations
- The xISS Turbo instruction set simulator runs at up to 200MHz, enabling fast development, software test and debug. Functionally accurate, xISS is designed to enable software development when hardware is unavailable: for instance prior to first silicon, or when cost or supply issues restrict the availability of prototypes or emulation hardware.
- The VTOC modeling toolset produces cycle-accurate C++ and SystemC models from Verilog and VHDL RTL, allowing simulation of the entire SoC, including ARC and third-party IP.
- The ARCangel™ FPGA-based emulation system provides fast emulation capability
On-Chip Debug Features
Each core's JTAG interface allows a debug host to set software breakpoints, examine or change memory and register values, and step through the target code. Optional hardware breakpoints can be added.
Operating Systems
The ARC EP family is supported by industry standard operating system software from ARC and from third parties:
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